Semiconductor logic devices, which include a wide variety of types and applications, employ logic circuitry to manipulate or store input data and an output buffer to provide the manipulated or stored data at an output terminal of the device. Depending on the type of logic device and/or the circuit environment in which the device is used, the output buffer's output terminal can be connected to one or more input signals which provide a negative voltage level, often as low as -1 volt. For example, the output terminal (or "data terminal") of a memory device, such as a DRAM, is typically used to receive input signals as well as to provide output signals. In this application, when the memory device is in the "receive" or "write" mode, the output buffer is disabled so that it does not provide a voltage bias to the input signal at the data terminal. Similarly, the output terminal of a latch, although not necessarily having a "receive" mode, is typically connected to a signal-receiving data bus, and the output terminal of the latch is controlled, so as not to provide a voltage bias to the bus.
In either situation, when the output terminal is connected to an input signal which provides a negative voltage level as low as, e.g., -1 volt, certain transistors in the output buffer can be activated. For instance, the portion of the output buffer which provides the high-level logic signals at the terminal is typically coupled to transistors which are activated in response to such a negative voltage level being presented at the output terminal. The activated transistors can cause excessive substrate current to flow and excessive drain current to pass to ground (or common) through this portion of the output buffer (sometimes referred to as "pull-up" circuitry). This results in wasted current and, in some instances, causes the output buffer to latch-up and therefore fail.
One known approach for mitigating this problem is to implement the pull-up circuitry using two transistor devices in series rather than one transistor by itself. Because the drain-source voltage across each of the two devices is reduced, the conduction of current is reduced by the same factor. A disadvantage in this approach, however, is that by doubling the number of transistors in series, the device widths must also be doubled in order to get the same drive--that requires four times as much current to drive these devices but still results in the same output current and four times as much space. Moreover, to accommodate the same level of current drive through the series-arranged transistors, the width requirement for manufacturing each transistor is effectively doubled, which represents a four-fold increase in terms of semiconductor space. Further, control circuits, including large capacitors, are often used in this arrangement to drive the series-arranged transistors, and this requires more space and impairs the speed of the output buffer. Thus, this approach is burdensome in terms of space, speed, and current consumption.
Another approach is to implement the pull-up circuitry using one pull-up device, but with an additional transistor device and resistor arranged to bias the input (or gate) of the pull-up device to a low-level voltage in response to such a negative voltage level being presented at the output terminal. This approach reduces the gate-source voltage across the pull-up device and thereby slightly reduces the substrate current and slightly reduces the consumption of drain current during this condition. Unfortunately, the extent of current reduction is relatively insubstantial. In addition, the pull-up device is still active when the negative voltage level is present at the output terminal, and this causes excess current to be drawn from other devices through the output terminal.
The above-mentioned problems are believed to have been discovered in connection with the conception and implementation of the present invention, which provides a number of features and advantages, including solutions to these problems.